We decided to implement our circuit as a PCB shield for the STM Discovery Board for ease of use.

 

It is a four layer board, with the top layer for components and critical routing, the second layer for ground, and the third and fourth layers for additional routing, with the third layer containing a large polygon for distribution of the high voltage bus and the fourth layer containing a large polygon for distributing the 12V bus. 

 

Organizationally, the circuit is split left/right, with the right side containing the high power paths and the the left side containing the sense circuitry and user interface components. To help with debugging, a large number of test point pads are distributed across the board.

 

The FETs are all thermally tied together with a bar of aluminum as a heatsink. Each FET is screwed into the aluminum block and is electrically isolated by mica pads and a rubber grommet.

 

Top Layer:

Component placement is extremely important, especially when high power or delicate analog sensing is involved. The power path on the right was optimized to have wide, short traces without a tortuous path. The gate drivers are located physically extremely close to the FET gates. For optional filtering, there are pads next to the current sense resistor for capacitors. 

 

The high voltage input is located near the top of the board so that it is nearer the FET drains, and the rest of the board is powered from a 12V input at the bottom of the board. A 5V LDO generates 5V (as a convenience for any other 5V peripherals on the Discovery board), and the regulator on the Discovery board generates 3V for the amplifier supplies.

 

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Second Layer:

The ground plane is split into two halves to isolate the high power path from the rest of the circuitry. The two grounds are connected by a split in the middle of the board. The ground plane is otherwise only used for the routing of two traces, one at the very periphery of the board, and one very short trace not located near critical components.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Third Layer:

This layer is mainly used for extra routing in dense areas. It also contains a connection between the high power ground input and the 12V ground inputs (wide trace at far left of board) and  a polygon for high voltage distribution (top right).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bottom Layer:

The bottom layer contains the route for 12V to reach the gate drivers and the bulk of the routing of the current sense lines (as far away from the switching node as possible while still remaining a direct route).